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ATR4256
4.6
DAC1, DAC2 in FM Mode (Pin 3 and Pin 4)
The gains of DAC1 and DAC2 have a range of 0.69 × V (PDO) to 2.16 × V (PDO) . V (PDO) is the PLL
tuning voltage output. This range is divided into 256 steps; one step is approximately
(2.16 – 0.46) × V (PDO) / 255 = 0.005764 × V (PDO) . The gain of DAC1 can be controlled by B36 to
B43 (bits 0 to 7 of DAC1 Gain), and the gain of DAC2 by B0 to B7 (bits 0 to 7 of DAC2 Gain) as
follows:
Table 4-4.
DAC Gain Setting, FM Mode
Gain DAC1,
Decimal
Approximately
B43
B42
B41
B40
B39
B38
B37
B36
Gain
Gain DAC2,
Decimal
Approximately
0.69 × V (PDO)
0.69576 × V (PDO)
0.70153 × V (PDO)
0.70729 × V (PDO)
...
0.99549 × V (PDO)
...
2.14847 × V (PDO)
2.15424 × V (PDO)
2.16 × V (PDO)
B7
0
0
0
0
...
0
...
1
1
1
B6
0
0
0
0
...
0
...
1
1
1
B5
0
0
0
0
...
1
...
1
1
1
B4
0
0
0
0
...
1
...
1
1
1
B3
0
0
0
0
...
0
...
1
1
1
B2
0
0
0
0
...
1
...
1
1
1
B1
0
0
1
1
...
0
...
0
1
1
B0
0
1
0
1
...
1
...
1
0
1
Gain
0
1
2
3
...
53
...
253
254
255
Offset = 31 (intermediate position)
The offset of DAC1 and DAC2 has a range of 0.56V to –0.59V. This range is divided into 64
steps; one step is approximately 1.15V / 63 = 18.25 mV. The offset of DAC1 can be controlled
by B44 to B49 (bits 0 to 5 of DAC1 Offset), and the offset of DAC2 by B8 to B13 (bits 0 to 5 of
DAC2 Offset) as follows:
Table 4-5.
DAC Offset Setting, FM Mode
Offset DAC1,
Decimal
Approximately
B49
B48
B47
B46
B45
B44
Gain
Offset DAC2,
Decimal
Approximately
0.56V
0.5417V
0.5235V
0.5052V
...
+0.0059V
...
0.5535V
–0.5717V
–0.59V
B13
0
0
0
0
...
0
...
1
1
1
B12
0
0
0
0
...
1
...
1
1
1
B11
0
0
0
0
...
1
...
1
1
1
B10
0
0
0
0
...
1
...
1
1
1
B9
0
0
1
1
...
1
...
0
1
1
B8
0
1
0
1
...
1
...
1
0
1
Gain
0
1
2
3
...
31
...
61
62
63
Gain = 53 (intermediate position)
7
4867D–AUDR–01/08
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